Title:
電圧安定化回路及び制御方法
Document Type and Number:
Japanese Patent JP4167225
Kind Code:
B2
Abstract:
The present invention relates to a voltage stabilizer that stabilizes the voltage of a power supply line on a semiconductor substrate and is intended to provide a voltage stabilizer having a small mounting area on the semiconductor substrate, capable of stabilizing the voltage of the power supply path connecting the power supply and semiconductor substrate. The voltage stabilizer includes a monitoring section 110 connected to the power supply line Vdd that monitors the potential of the power supply line Vdd and outputs a monitor signal indicating the monitoring result and a first current control section 120 that passes a current from the power supply line Vdd according to the monitor signal to stabilize the voltage of the power supply line Vdd, capable of freely passing a current continuously.
Inventors:
Yuki Ozeki
Toshige Ando
Toshige Ando
Application Number:
JP2004542783A
Publication Date:
October 15, 2008
Filing Date:
October 08, 2002
Export Citation:
Assignee:
富士通株式会社
International Classes:
G05F3/24; G05F1/613; H03F3/343
Domestic Patent References:
| JP5035349A | ||||
| JP2000047740A |
Foreign References:
| US20020135339 | ||||
| US6069521 |
Attorney, Agent or Firm:
Masaki Yamada
Mikami Yui
Mikami Yui
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