Title:
半導体装置の出力回路調整方法
Document Type and Number:
Japanese Patent JP4199789
Kind Code:
B2
Abstract:
An output circuit of a semiconductor includes unit buffers, each unit buffer having transistors and resistors connected between a power source terminal VDDQ and an output terminal DQ, and transistors and resistors connected between a power source terminal VSSQ and an output terminal DQ. On-resistance values of transistors included in the unit buffers are mutually substantially the same, and resistance values of resistors included in the unit buffers are mutually different. A deviation of impedances attributable to a power source resistance can be offset based on a difference between resistance values of the resistors.
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Inventors:
Hiroto Kinoshita
Hiroki Fujisawa
Hiroki Fujisawa
Application Number:
JP2006232083A
Publication Date:
December 17, 2008
Filing Date:
August 29, 2006
Export Citation:
Assignee:
Elpida Memory Co., Ltd.
International Classes:
H03K19/0175
Domestic Patent References:
| JP2006203405A | ||||
| JP2006115489A | ||||
| JP2000031811A | ||||
| JP8032435A |
Attorney, Agent or Firm:
Mitsuhiro Washito
Ogata Japanese
Ogata Japanese
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