メモリ制御装置

Title:

メモリ制御装置

Document Type and Number:

Japanese Patent JP4208541

Kind Code:

B2

Abstract:

A memory controller reads data from DRAM at a request from a plurality of masters. It includes a prefetch buffer for storing a result of a pre-reading operation, and a register for setting a specific master among a plurality of masters. When a master requests a read, the memory controller pre-reads data subsequent to the requested data, and determines whether or not the master is a specific master set by the register. If the master is the specific master set by the register, then the result of the pre-read is stored in the prefetch buffer. Thus, the prefetch buffer can effectively function in a system having a plurality of masters.

Inventors:

Toshiaki Minami

Application Number:

JP2002285577A

Publication Date:

January 14, 2009

Filing Date:

September 30, 2002

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