Title:
フローティングゲート不揮発性メモリデバイスの製造方法
Document Type and Number:
Japanese Patent JP4223551
Kind Code:
B2
Abstract:
The invention relates in particular, though not exclusively, to an integrated circuit with an embedded non-volatile memory with floating gate (10). According to the invention, at least two poly layers of equal or at least substantially equal thickness are used for this device. The first poly layer, poly A, is for the floating gate (10) and for the gates (22) of NMOS and PMOS in the logic portion of the circuit. The second poly layer, poly B, serves exclusively for the control electrode (21) above the floating gate. If so desired, a third poly layer may be deposited for both the control electrode and the logic gates, so that the thicknesses of these electrodes, and thus their resistances, are given desired values. Problems like overetching and bridging during saliciding are prevented in that the control electrode and the logic gates have the same thickness.
Inventors:
Dolmans gido joseph maria
Ferhard Robertas Dominicus Joseph
Kuppens Roger
Ferhard Robertas Dominicus Joseph
Kuppens Roger
Application Number:
JP53417497A
Publication Date:
February 12, 2009
Filing Date:
March 10, 1997
Export Citation:
Assignee:
NXP B.V.
International Classes:
H01L21/8247; H01L21/28; H01L21/336; H01L27/10; H01L27/105; H01L27/115; H01L29/423; H01L29/43; H01L29/788; H01L29/792
Domestic Patent References:
| JP5136424A | ||||
| JP4348072A | ||||
| JP5183134A | ||||
| JP2003985A | ||||
| JP61111581A |
Attorney, Agent or Firm:
Kenji Sugimura
Tatsuya Sawada
Tatsuya Sawada