可変閾スライサ段を備える受信機及び該スライサ段の閾レベルを更新する方法

Title:

可変閾スライサ段を備える受信機及び該スライサ段の閾レベルを更新する方法

Document Type and Number:

Japanese Patent JP4228050

Kind Code:

B2

Abstract:

A receiver having a variable bit slicer for detecting bits in a demodulated signal, comprises a demodulator ( 14 ) for deriving a demodulated bit rate signal, means ( 36 ) for storing a plurality of threshold values, each of the threshold values being selectively adjustable, means ( 28, 38 ) for selecting the threshold value for comparison with the current bit signal (S_n) in response to a sequence of N bits (where N is at least 2) (B_n-1, B_n-2) received prior to the current bit (B_n) and means ( 38, 40 ) for using the current bit to update the selected threshold value. Also disclosed is a method of dc offset correction.

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Inventors:

Payne Adrian W
Moor Paul A
Minnis Brian Jay

Application Number:

JP2002555055A

Publication Date:

February 25, 2009

Filing Date:

December 21, 2001

Export Citation:

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Assignee:

NXP B.V.

International Classes:

H04L25/03; H04L25/06

Domestic Patent References:

JP8107429A
JP8331183A
JP60208145A
JP61273050A
JP60176324A
JP61193542A

Attorney, Agent or Firm:

Kenji Yoshitake
Hidetoshi Tachibana
Takeshi Sekine
Takahashi

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