Title:
ビット線デコーダ回路、ビット線接続手段、及びビット線選択方法
Document Type and Number:
Japanese Patent JP4263431
Kind Code:
B2
Abstract:
A bit line decoder scheme is described that connects data and voltage to a plurality of bit lines of a dual bit flash memory array. The bit lines are connected to a plurality of intermediate data lines by a first decoder unit and the intermediate data lines are connected to a plurality of data lines of the sense amplifiers by a second decoder unit. In one embodiment the voltage is connected to a selected bit line through a separate decoder unit and in a second embodiment the voltage is connected through the decoder unit connected to the intermediate data lines.
Inventors:
Tomoko Ogura
Application Number:
JP2002197394A
Publication Date:
May 13, 2009
Filing Date:
July 05, 2002
Export Citation:
Assignee:
Halo LSI Inc.
International Classes:
G11C16/06; G11C7/18; G11C8/10; G11C16/02; G11C16/04; G11C16/08; G11C16/24
Domestic Patent References:
| JP2000057794A | ||||
| JP7057487A | ||||
| JP10027482A |
Foreign References:
| US6081456 |
Other References:
Hayashi, Y. et al.,Twin MONOS cell with dual control gates,VLSI Technology, 2000. Digest of Technical Papers,米国,IEEE,2000年 6月15日,p.122 - 123
Attorney, Agent or Firm:
Kaori Tanaka
Michito Hiraki
Sanji Tanabe
Michito Hiraki
Sanji Tanabe