Title:
半導体集積回路装置
Document Type and Number:
Japanese Patent JP4322645
Kind Code:
B2
Abstract:
There is achieved a high-integrated and high-speed nonvolatile memory which can stabilize an operation of a phase-change memory for a short operation cycle time. A latch is provided in a write driver. A change to a high-resistance state of a phase-change element is performed per column cycle by a write-enable signal, and a change to a low-resistance state thereof is performed after a pre-charge command is inputted and concurrently with deactivation of a pre-charge signal. Thereby, a write time to a memory cell in which phase-change resistance is changed to a low-resistance state, and a period from a write operation for changing the phase-change resistance to a high-resistance state to a read operation to the above memory cell can be lengthened without extending the column cycle time, so that the stable write operation is achieved.
Inventors:
Riichiro Takemura
Ken Sakata
Norikatsu Takaura
Kazuhiko Kajitani
Ken Sakata
Norikatsu Takaura
Kazuhiko Kajitani
Application Number:
JP2003398398A
Publication Date:
September 02, 2009
Filing Date:
November 28, 2003
Export Citation:
Assignee:
株式会社日立製作所
エルピーダメモリ株式会社
エルピーダメモリ株式会社
International Classes:
G11C11/42; G11C13/00; G11C5/00; G11C7/00; G11C8/08; G11C11/419; G11C13/02
Domestic Patent References:
| JP4111291A |
Attorney, Agent or Firm:
Yamato Tsutsui