Title:
バイアス電圧発生回路
Document Type and Number:
Japanese Patent JP4374254
Kind Code:
B2
Abstract:
A bias circuit, which generates a bias voltage, has a first MOS transistor coupled between a first reference voltage terminal and a voltage dividing node and a second MOS transistor coupled in parallel with the first MOS transistor. The first MOS transistor may have a first ON-state resistance, and the second MOS transistor may have a second ON-state resistance which is lower than the first ON-state resistance. Furthermore, the bias circuit has a resistance circuit coupled between the voltage dividing node and a second reference voltage terminal and a voltage generator coupled with the first node. The voltage generator outputs the bias voltage in dependence upon an electrical potential on the voltage dividing node.
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Inventors:
Shuichiro Fujimoto
Application Number:
JP2004018388A
Publication Date:
December 02, 2009
Filing Date:
January 27, 2004
Export Citation:
Assignee:
oki Semiconductor Co., Ltd.
Oki Micro Design Co., Ltd.
Oki Micro Design Co., Ltd.
International Classes:
H01L27/04; H03F1/00; G05F3/20; G05F3/24; G05F3/26; H01L21/822; H02J1/00; H03F3/72
Domestic Patent References:
| JP8171432A | ||||
| JP8314560A | ||||
| JP10163834A | ||||
| JP2003256056A | ||||
| JP2001285069A | ||||
| JP7042566U |
Attorney, Agent or Firm:
Kakimoto Yasunari