Title:
LSI,LSIを搭載した電子装置、デバッグ方法、LSIのデバッグ装置
Document Type and Number:
Japanese Patent JP4409056
Kind Code:
B2
Abstract:
Authentication circuits (2-3 to 2-11) are provided between a debug I/F circuit (2-1) and a debug terminal. The authentication circuit transmits a transmission key to externally at the time of activation, and authenticates from a received signal and the transmission key, and enables to access a debug I/F. It is possible to prevent a spurious access from the debug I/F by a third person by the authentication circuit.
Inventors:
Yusuke Kawasaki
Shigeru Hashimoto
Shigeru Hashimoto
Application Number:
JP2000199266A
Publication Date:
February 03, 2010
Filing Date:
June 30, 2000
Export Citation:
Assignee:
富士通株式会社
富士通フロンテック株式会社
富士通フロンテック株式会社
International Classes:
G06F11/22; G06F11/36; G06F21/12; G01R31/317
Domestic Patent References:
| JP2001264396A |
Attorney, Agent or Firm:
Hayashi Tsunetoku
Kenji Doi
Kenji Doi