Title:
全ての出力をモニタリングすることなしに主ATX出力をアクセスする方法
Document Type and Number:
Japanese Patent JP4472106
Kind Code:
B2
Abstract:
A power monitor circuit method delays the start of a computer until multiple power lines are at a safe level of operation. The integrated circuit monitors only the voltage of a primary power supply output and eliminates the need for monitor on each supply. The power supply is made to exacting specifications that tie the 5 volt and 3.3 volt supplies to the primary 12 volt supply. The ATX power supply drives the 3.3 and 5.0 supplies to reach 90% of their values within 40 ms after the 12 volt supply reaches 90% of its value. A time delay circuit 25 delays switching the 3.3 and 5 volt dual supply from the standby voltage supply to the active voltage supply until after the primary 3.3 and 5 volt are at a safe operating level.
Inventors:
Bogdan Duduman
Application Number:
JP2000123203A
Publication Date:
June 02, 2010
Filing Date:
April 24, 2000
Export Citation:
Assignee:
Intersil Corporation
International Classes:
G06F1/28
Domestic Patent References:
| JP6175752A | ||||
| JP7325638A |
Attorney, Agent or Firm:
Tadao Hirata