Title:
データ処理装置
Document Type and Number:
Japanese Patent JP4492035
Kind Code:
B2
Abstract:
Each of memory bridges (16, 26) and I/O bridges (18, 28), cross-linked to one another, is provided with an interface circuit section which performs data transmission and reception according to an PCI-Express interface. Each interface circuit section has a communication error processing section. When an error occurs in data received from the I/O bridge (18), the communication error processing section of the memory bridge (16) cancels the received data and sends a communication error signal to the memory bridge (26). When receiving the communication error signal, the memory bridge (26) stops receiving the data. Then, the communication error processing section of the memory bridge (16) requests the I/O bridge (18) to resend data.
Inventors:
Fumitoshi Mizutani
Oda Shinya
Oda Shinya
Application Number:
JP2003115621A
Publication Date:
June 30, 2010
Filing Date:
April 21, 2003
Export Citation:
Assignee:
NEC
International Classes:
G06F11/14; G06F11/18; G06F11/07; G06F13/00; G06F13/38; G06F13/40; G06F15/16; G06F15/177; H04L1/08; H04L12/26; G06F11/16
Domestic Patent References:
| JP2001526422A | ||||
| JP2001290668A | ||||
| JP10154085A | ||||
| JP2264337A | ||||
| JP1154242A | ||||
| JP11296394A | ||||
| JP4071037A | ||||
| JP8278950A |
Attorney, Agent or Firm:
Kimura Mitsuru