Title:
記憶システム及びそのデータコピー方法
Document Type and Number:
Japanese Patent JP4504138
Kind Code:
B2
Abstract:
A memory system includes a memory cell array, a bit line switch, first and second page buffers, a column switch, an error correction circuit, and control circuits. The second page buffer can swap data with the first page buffer. The control circuits controls the bit line switch and the first and second page buffers, sequentially reads, page by page, one or more pages from the mth (m is a positive integer) page to the nth (n is an integer greater than m) page of the first block in the memory cell array, controls the error correction circuit to perform error correction calculation by the error correction circuit, controls the first and second data buffers and the bit line switch, and controls to perform write in the second block in the erase state in the memory cell array.
Inventors:
Hitoshi Shiga
In the process of listing
Tomohiro Wang
Hong Seongrin
In the process of listing
Tomohiro Wang
Hong Seongrin
Application Number:
JP2004257565A
Publication Date:
July 14, 2010
Filing Date:
September 03, 2004
Export Citation:
Assignee:
Toshiba Corporation
Solid state system
Solid state system
International Classes:
G11C16/02; G11C16/06
Domestic Patent References:
| JP2004507007A | ||||
| JP2003233992A | ||||
| JP2004118940A | ||||
| JP2003187583A |
Attorney, Agent or Firm:
Takehiko Suzue
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto