Title:
高次基数のLOGMAPプロセッサ
Document Type and Number:
Japanese Patent JP4520122
Kind Code:
B2
Abstract:
A Log Map processor that processes information in accordance with the Log MAP algorithm using an N-state Radix-K trellis where K is an integer equal to 4 or greater and N is an integer equal to 2 or greater, wherein K branches enter and leave each trellis state. The Log Map processor comprises branch and path metric calculators designed with LogSum operators. The LogSum operators used and Add-Compare-Select architecture that is based on an approximation of the Jacobian definition of the LogSum operation. The Log Map processor is thus able to process relatively more information per unit time.
Inventors:
Mark Andrew Vicker Staff
Linda Marie Davis
Linda Marie Davis
Application Number:
JP2003296369A
Publication Date:
August 04, 2010
Filing Date:
August 20, 2003
Export Citation:
Assignee:
Alcatel-Lucent USA Inc.
International Classes:
G06F17/18; H03M13/41; H03M13/29; H03M13/39; H04L1/00
Domestic Patent References:
| JP2002208219A | ||||
| JP2002076920A | ||||
| JP6290164A | ||||
| JP11095786A | ||||
| JP2002176366A |
Other References:
Arun Raghupathy et al.,A Transformation for Computational Latency Reduction in Turbo-Map Decoding,Proceedings of the 1999 IEEE International Symposium on Circuits and Systems (ISCAS '99),IEEE,1999年 6月,Vol.1,pp.402-405
Guido Masera et al.,VLSI Architecture for Turbo Codes,IEEE Transactions on Very Large Scale Integration (VLSI) Systems,IEEE,1999年 9月,Vol.7, No.3,pp.369-379
Guido Masera et al.,VLSI Architecture for Turbo Codes,IEEE Transactions on Very Large Scale Integration (VLSI) Systems,IEEE,1999年 9月,Vol.7, No.3,pp.369-379
Attorney, Agent or Firm:
Masao Okabe
Nobuaki Kato
Kazuo
Shinichi Usui
Ikuo Fujino
Takao Ochi
Teruhisa Motomiya
Norimichi Takanashi
Asahi Shinmitsu
Seiichiro Takahashi
Koji Yoshizawa
Nobuaki Kato
Kazuo
Shinichi Usui
Ikuo Fujino
Takao Ochi
Teruhisa Motomiya
Norimichi Takanashi
Asahi Shinmitsu
Seiichiro Takahashi
Koji Yoshizawa