Title:
自己整列を利用したBiCMOSの製造方法
Document Type and Number:
Japanese Patent JP4532131
Kind Code:
B2
Abstract:
Provided is a method for manufacturing a self-aligned BiCMOS including a SiGe heterojunction bipolar transistor (HBT) for performing high-frequency operations. In this method, an extrinsic base and a selective ion-implanted collector (SIC) are formed by a self-alignment process.
Inventors:
Lee Satoshi
Shrine
Shrine
Application Number:
JP2004029803A
Publication Date:
August 25, 2010
Filing Date:
February 05, 2004
Export Citation:
Assignee:
SAMSUNG ELECTRONICS CO.,LTD.
International Classes:
H01L21/331; H01L21/8222; H01L21/8248; H01L21/8249; H01L27/04; H01L27/06; H01L29/737
Domestic Patent References:
| JP2001244275A | ||||
| JP2000031156A | ||||
| JP2001196385A | ||||
| JP2002270819A | ||||
| JP2002329725A | ||||
| JP9186172A | ||||
| JP7153772A | ||||
| JP4184937A | ||||
| JP4233236A | ||||
| JP4005851A | ||||
| JP2001035858A | ||||
| JP4137528A | ||||
| JP6069434A |
Attorney, Agent or Firm:
Mikio Hatta
Atsushi Nogami
Yasuo Nara
Etsuko Saito
Katsuyuki Utani
Toshifumi Fujii
Atsushi Nogami
Yasuo Nara
Etsuko Saito
Katsuyuki Utani
Toshifumi Fujii