Title:
半導体装置の製造方法
Document Type and Number:
Japanese Patent JP4592837
Kind Code:
B2
Abstract:
A semiconductor device having a highly reliable groove isolation structure with a desired radius of curvature formed at the groove upper edge and without formation of any step, there is produced by reducing the stress generation around the groove upper edge of an element isolation groove on a semiconductor substrate, thereby optimizing the shape of an element isolation groove and making the device finer and improving the device electric characteristics.
Inventors:
Norio Ishizuka
Hideo Miura
Shuji Ikeda
Yasuko Yoshida
Norio Suzuki
Kojima Masayuki
Kota Funayama
Hideo Miura
Shuji Ikeda
Yasuko Yoshida
Norio Suzuki
Kojima Masayuki
Kota Funayama
Application Number:
JP21683198A
Publication Date:
December 08, 2010
Filing Date:
July 31, 1998
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L21/76; H01L21/762; H01L29/78
Domestic Patent References:
| JP2260660A | ||||
| JP9129720A | ||||
| JP2083928A | ||||
| JP9293714A | ||||
| JP11145273A |
Attorney, Agent or Firm:
Polaire Patent Business Corporation