Title:
位相同期回路
Document Type and Number:
Japanese Patent JP4629310
Kind Code:
B2
Abstract:
A variable loop bandwidth phase locked loop in which, upon input of a succession of signals "1", no modulated signal degradation occurs and even at a high symbol rate, the reference signal frequency remains low and the sampling frequencies of a phase-frequency detector and a sigma delta circuit remain low. The phase locked loop comprises: a first modulator which transforms baseband signal TX_DATA into an integer signal for specifying a division number and sends it to a control terminal of a programmable divider; a second modulator which shapes an incoming baseband signal into a prescribed signal waveform and sends it to a voltage controlled oscillator; and a variable current charge pump which changes the loop bandwidth of the phase locked loop according to control signal CUR.
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Inventors:
Sadayuki Shibahara
Yu Kokubo
Shun Oshima
Yu Kokubo
Shun Oshima
Application Number:
JP2003020459A
Publication Date:
February 09, 2011
Filing Date:
January 29, 2003
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H03L7/093; H03C3/09; H03L7/06; H03L7/089; H03L7/107; H03L7/197; H04L7/033
Domestic Patent References:
| JP7086930A | ||||
| JP2001237709A | ||||
| JP2001517013A | ||||
| JP58085628A |
Foreign References:
| EP0408238A1 |
Attorney, Agent or Firm:
Polaire Patent Business Corporation
Katsuo Ogawa
Katsuo Ogawa