Title:
不揮発性半導体メモリ
Document Type and Number:
Japanese Patent JP4633958
Kind Code:
B2
Abstract:
A non-volatile flash memory (100) that may have an improved layout freedom is disclosed. Non-volatile flash memory (100) may include banks (B0 and B1). Each bank (B0 and B1) may include memory cell arrays (MCA00 to MCA03) including a plurality of memory cells (MC) connected to sub bit lines (LB). A plurality of sub bit lines (LB) may be selectively connected to a main bit line (MB) by a group switch (Y1S0 and Y1S1). A group of main bit lines (MB) may be disposed over a memory cell array. A group of main bit lines (MB) may be selectively connected to a sense amplifier block (SAB) by a group switch group (Y2S0 and Y2S1) and a bank switch group (Y3S0 and Y3S1). In this way, a sense amplifier block (SAB) may be shared by a plurality of groups of main bit lines (MB). In this way, layout freedom may be improved.
Inventors:
Hiroshi Sugawara
Jimbo agile
Atsushi Miki
Takayuki Kurokawa
Ushikoshi Kenichi
Jimbo agile
Atsushi Miki
Takayuki Kurokawa
Ushikoshi Kenichi
Application Number:
JP2001135774A
Publication Date:
February 16, 2011
Filing Date:
May 07, 2001
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
G11C16/06; G11C5/02; G11C7/18
Domestic Patent References:
| JP10209304A | ||||
| JP2000293994A | ||||
| JP2001052495A | ||||
| JP9017979A |
Attorney, Agent or Firm:
Kimura Mitsuru