Title:
ウエハにおける欠陥を検知する方法及び装置
Document Type and Number:
Japanese Patent JP4657394
Kind Code:
B2
Abstract:
A method for detecting electrical defects in a semiconductor wafer. includes the steps of: a) applying charge to the wafer such that electrically isolated structures are raised to a voltage relative to electrically grounded structures; b) obtaining voltage contrast data for at least a portion of the wafer containing such structures using an electron beam; and c) analyzing the voltage contrast data to detect structures at a voltages different to predetermined voltages for such structures. Voltage contrast data can take one of a number of forms. In a simple form. data for a number of positions on a line scan of an electron beam can be taken and displayed or stored as a series of voltage levels and scan positions. Alternatively. the data from a series of scans can he displayed as a voltage contrast image. Analysis can be achieved by comparison of one set of voltage contrast data. for example voltage contrast data from one die on a wafer. with one or more other such sets. for example voltage contrast data for corresponding structures on one or more preceding dice. so as to determine differences therebetween.
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Inventors:
Christopher Graham Talbot
Chiwoei Wayne Ro
Louis Camilo Olhuera
Lee Won
Chiwoei Wayne Ro
Louis Camilo Olhuera
Lee Won
Application Number:
JP468998A
Publication Date:
March 23, 2011
Filing Date:
January 13, 1998
Export Citation:
Assignee:
SCHLUMBERGER TECHNOLOGIES,INCORPOATED
International Classes:
G01N23/225; H01L21/66; G01N21/88; G01N21/956; G01N27/60; G01R1/06; G01R31/302; G01R31/307; H01J37/28
Domestic Patent References:
| JP2280071A |
Attorney, Agent or Firm:
Masaaki Kobashi