Title:
メモリコントローラ、フラッシュメモリシステム及びフラッシュメモリの制御方法
Document Type and Number:
Japanese Patent JP4661191
Kind Code:
B2
Abstract:
To improve processing efficiency when accessing a flash memory.
A plurality of sector regions specified by a logic address and the number of sectors supplied along with a read command from a host system are divided into groups for each logic group in a step 1, a physical address corresponding to a start sector in the first group is obtained in a step 2, and reading is started with the first group as a target in a step 4. Then, in a step 5, a physical address corresponding to the start sector in the next group is obtained without waiting for the completion of a read sequence processing started in the step 4. In a step 7, reading is started with the next group as a target.
COPYRIGHT: (C)2006,JPO&NCIPI
Inventors:
Yukio Terasaki
Application Number:
JP2004346576A
Publication Date:
March 30, 2011
Filing Date:
November 30, 2004
Export Citation:
Assignee:
tdk Corporation
International Classes:
G06F12/06; G06F12/00; G06F12/02
Domestic Patent References:
| JP2004070691A | ||||
| JP2000284996A |
Attorney, Agent or Firm:
Kimura Mitsuru
Takanori Mamoru
Takanori Mamoru