Title:
半導体記憶装置
Document Type and Number:
Japanese Patent JP4667888
Kind Code:
B2
Abstract:
Provided is a semiconductor memory device compatible with a SRAM and capable of a high-speed data transfer operation while maintaining data reliability. An access to a memory core 6 starts when an external chip enable signal XCE performs a falling transition. Simultaneously, an external write enable signal XWE and an external address signal ADD are received, and a memory cell 1, in the memory core 6, corresponding to the received external address signal ADD is selected. When a data read-out from the memory cell 1 or a data write-in to the memory cell 1 is complete, a rewrite timer 7 is activated in accordance with a rising transition of an external chip enable signal XCE or a rising transition of the external write enable signal XWE for performing a data rewrite for the memory cell 1.
Inventors:
Shunichi Iwanari
Masahiko Sakagami
Hiroshige Hirano
Tetsuji Nakakuma
Takashi Miki
Gogo Yasushi
Kunio Yamaoka
Yasuo Murakuki
Masahiko Sakagami
Hiroshige Hirano
Tetsuji Nakakuma
Takashi Miki
Gogo Yasushi
Kunio Yamaoka
Yasuo Murakuki
Application Number:
JP2005025222A
Publication Date:
April 13, 2011
Filing Date:
February 01, 2005
Export Citation:
Assignee:
Panasonic Corporation
International Classes:
G11C11/403; G11C11/22; G11C11/401; G11C11/4076; G11C11/4091
Domestic Patent References:
| JP2001357667A | ||||
| JP8273375A | ||||
| JP2004139719A | ||||
| JP11086566A | ||||
| JP3152789A | ||||
| JP2003317471A | ||||
| JP2005011485A | ||||
| JP1130391A | ||||
| JP2004342219A | ||||
| JP61042797A | ||||
| JP60193197A | ||||
| JP60136089A |
Attorney, Agent or Firm:
Shiro Ogasawara