To provide a semiconductor test device and method and a simulation device for semiconductor test capable of easily performing cause investigation at low cost when in fail by enabling various timings to be set to negative values without a large increase of costs.
A timing setting value calculation part 22 calculates setting values of various timing based on a test program P10 with which at least one of rise-up and fall timings of test signals T1-Tn and quality determination timing of a signal acquired from a semiconductor device 30 is specified. An adding part 23 adds offset quantity specified in the test program P10 for a set value determined in the timing setting value calculation part 22. The setting value to which the offset quantity is added is set in a register 16, and a signal generation device 11 generates the test signals T1-Tn and a strobe signal ST at the timing according to the set content of the register 16.
COPYRIGHT: (C)2008,JPO&INPIT
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Tadashi Takahashi
Takashi Watanabe
Masakazu Aoyama
Suzuki Mitsuyoshi
Kazuya Nishi
Yasuhiko Murayama