Title:
薄膜トランジスタ表示板とその製造方法
Document Type and Number:
Japanese Patent JP4731897
Kind Code:
B2
Abstract:
A method of manufacturing a thin film transistor array panel is provided, which includes: forming a gate line on a substrate; depositing a first insulating layer and a semiconductor layer in sequence on the gate line; depositing a conductive layer on the semiconductor layer; photo-etching the conductive layer and the semiconductor layer; depositing a second insulating layer; photo-etching the second insulating layer to expose first and second portions of the conductive layer; forming a pixel electrode on the first portion of the conductive layer; removing the second portion of the conductive layer to expose a portion of the semiconductor layer; and forming a light blocking member on the exposed portion of the semiconductor layer, the light blocking member having an opening exposing the pixel electrode.
Inventors:
Nozomi Kim
Application Number:
JP2004354846A
Publication Date:
July 27, 2011
Filing Date:
December 08, 2004
Export Citation:
Assignee:
Samsung Electronics Company Limited
International Classes:
G02F1/1368; G02F1/136; G02F1/1362; G03G15/09; G09F9/30; H01L21/00; H01L21/3205; H01L21/336; H01L23/52; H01L29/786
Domestic Patent References:
| JP2002107762A | ||||
| JP2000089240A | ||||
| JP2001100652A | ||||
| JP10319430A | ||||
| JP9068723A |
Attorney, Agent or Firm:
Mikio Hatta
Yasuo Nara
Katsuyuki Utani
Ken Fujita
Masanori
Toshihiro Hasegawa
Yasuo Nara
Katsuyuki Utani
Ken Fujita
Masanori
Toshihiro Hasegawa