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Title:
半導体モジュール
Document Type and Number:
Japanese Patent JP4744071
Kind Code:
B2
Abstract:

To solve the reliability problem of a semiconductor device employing a thin and lightweight package caused by the warp of the package or the difference of thermal expansion coefficient between the device and a mounting board, e.g. the breaking of a conduction line provided in the semiconductor device or the failure of connection with a thin metal wire.

The conduction line 40 composed of a crystal larger in the X axis-Y axis direction than in the Z axis direction is buried in an insulating resin 44 and the back of the conduction line 40 is exposed from the insulating resin 44 thus providing a sealed semiconductor device. The breaking of the conduction line 40 buried in the insulating resin 44 is thereby suppressed.

COPYRIGHT: (C)2004,JPO


Inventors:
Noriaki Sakamoto
Yoshiyuki Kobayashi
Junji Sakamoto
Shigeaki Mashita
Katsumi Okawa
Eiju Maehara
Koji Takahashi
Application Number:
JP2003342077A
Publication Date:
August 10, 2011
Filing Date:
September 30, 2003
Export Citation:
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Assignee:
Sanyo Electric Co., Ltd.
International Classes:
H01L23/28; H01L23/50; H01L23/12; H01L25/00
Domestic Patent References:
JP9074149A
JP10152736A
JP11195742A
JP2002093847A
JP2002519848A
Foreign References:
WO1999067821A1
Attorney, Agent or Firm:
Takashi Okada
Katsuhiko Sudo



 
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