Title:
昇圧回路及びこれを内蔵する半導体装置
Document Type and Number:
Japanese Patent JP4746205
Kind Code:
B2
Abstract:
A boost voltage circuit includes a plurality of N channel type MOS transistors connected between an input terminal and an output terminal in series, wherein one electrode of each of the N channel type MOS transistors is connected to each of external terminals to which a capacitor can be connected to generate a boost voltage. A plurality of P channel type MOS transistors are respectively connected to each of the N channel type MOS transistors in parallel. Thereby, a boost voltage circuit with improved stability is provided so that the boost voltage circuit is started without increase of consumption current.
Inventors:
Hisamu Sato
Application Number:
JP2001177478A
Publication Date:
August 10, 2011
Filing Date:
June 12, 2001
Export Citation:
Assignee:
oki Semiconductor Co., Ltd.
Oki Micro Design Co., Ltd.
Oki Micro Design Co., Ltd.
International Classes:
G11C11/407; H02M3/07; G11C11/4074
Domestic Patent References:
| JP52022718A | ||||
| JP2001084783A | ||||
| JP9153778A |
Attorney, Agent or Firm:
Atsushi Nakajima
Kato Kazunori
Hiroshi Fukuda
Koichi Suzuki
Kato Kazunori
Hiroshi Fukuda
Koichi Suzuki