Title:
縦型トレンチゲート半導体装置およびその製造方法
Document Type and Number:
Japanese Patent JP4754353
Kind Code:
B2
Abstract:
A first region 11 functioning as a transistor includes a drain region 111, a body region 112 formed over the drain region 111, a source region 113A formed over the body region 112 and a trench formed through the body region 112 and having a gate electrode 120 buried therein. A source region 113B is formed over the body region 112 extending in a second region 12.
Inventors:
Shuji Mizoguchi
Mitsuhiro Yamanaka
Hiroyuki Gunji
Mitsuhiro Yamanaka
Hiroyuki Gunji
Application Number:
JP2005516414A
Publication Date:
August 24, 2011
Filing Date:
June 08, 2004
Export Citation:
Assignee:
Panasonic Corporation
International Classes:
H01L29/78; H01L21/331; H01L21/336; H01L21/8234; H01L29/06; H01L29/10; H01L29/739; H01L29/08; H01L29/417
Domestic Patent References:
| JP2003303967A | 2003-10-24 | |||
| JP2001085685A | 2001-03-30 | |||
| JP2002110978A | 2002-04-12 | |||
| JP2003017699A | 2003-01-17 | |||
| JPH1168107A | 1999-03-09 | |||
| JP2001094101A | 2001-04-06 | |||
| JP2001168333A | 2001-06-22 | |||
| JPH11243196A | 1999-09-07 |
Attorney, Agent or Firm:
Hiroshi Maeda
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Atsushi Fujita
Kazunari Ninomiya
Tomoo Harada
Iseki Katsumori
Seki Kei
Yasuya Sugiura
Hiroshi Takeuchi
Takahisa Shimada
Yuji Takeuchi
Katsumi Imae
Atsushi Fujita
Kazunari Ninomiya
Tomoo Harada
Iseki Katsumori
Seki Kei
Yasuya Sugiura