Title:
半導体集積装置、その設計方法、設計装置、およびプログラム
Document Type and Number:
Japanese Patent JP4803997
Kind Code:
B2
Abstract:
A semiconductor integrated device has a wire layout structure such that SL1≰SL2
Inventors:
Taro Sakurabayashi
Application Number:
JP2004350946A
Publication Date:
October 26, 2011
Filing Date:
December 03, 2004
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L21/82; G06F17/50
Domestic Patent References:
| JP5315335A | ||||
| JP2004158846A | ||||
| JP1291378A |
Attorney, Agent or Firm:
Kato Asamichi