Title:
バス・アクセス取り消しを伴うデータ処理システム
Document Type and Number:
Japanese Patent JP4848375
Kind Code:
B2
Abstract:
A bus master may selectively retract a currently pending access based on one or more characteristics of the currently pending access. In this manner, bus master may better control its access requests. The one or more characteristics may include, for example, type of access (e.g. read/write, instruction/data, burst/non-burst, etc.), sequence or order of accesses, address being accessed (e.g. which address range is being accessed or which device is being accessed), the bus master requesting retraction (in an, e.g., multimaster system), or any combination thereof. A bus arbiter may also selectively retract currently pending access requests in favor of a subsequent access request based on one or more characteristics of the currently pending access request or the subsequent access request. These characteristics may include any of those listed above, priorities of the requesting masters (e.g. a priority delta between requesting masters), other attributes of the requesting masters, or any combination thereof.
Inventors:
Moyer, William Sea.
Murdoch, Bullet W.
Murdoch, Bullet W.
Application Number:
JP2007534609A
Publication Date:
December 28, 2011
Filing Date:
September 01, 2005
Export Citation:
Assignee:
Freescale Semiconductor, Inc.
International Classes:
G06F13/36; G06F13/18
Domestic Patent References:
| JP2005025670A | 2005-01-27 | |||
| JP2005158035A | 2005-06-16 | |||
| JP2002063130A | 2002-02-28 | |||
| JPH06139188A | 1994-05-20 | |||
| JP2002041445A | 2002-02-08 |
Foreign References:
| US4987529A | 1991-01-22 |
Attorney, Agent or Firm:
Mamoru Kuwagaki