Title:
フリップフロップ回路
Document Type and Number:
Japanese Patent JP4851867
Kind Code:
B2
Abstract:
Signal delivery delay margin of a bypass flip-flop circuit is stabilized during high-frequency operation. An input controller for logically operating a bypass signal and a clock produces first and second output signals having different states depending on whether or not the bypass signal is activated. A latch circuit latches input data based on the first and second output signals. A latch controller logically operates the bypass signal and input data to generate a third output signal having a different state depending on whether or not the bypass signal is activated. An output controller is switched in response to the states of the first and second output signals for logically combining an output signal selected from the latch circuit and the third output signal to provide the output signal.
Inventors:
Kim respect Hun
Lu Lunhui
Lu Lunhui
Application Number:
JP2006182384A
Publication Date:
January 11, 2012
Filing Date:
June 30, 2006
Export Citation:
Assignee:
HYNIX SEMICONDUCTOR INC.
International Classes:
H03K3/3562; H03K3/037
Domestic Patent References:
| JP20065661A | ||||
| JP8195650A | ||||
| JP573703A | ||||
| JP563555A | ||||
| JP9270677A |
Foreign References:
| US5656962 |
Attorney, Agent or Firm:
Ichiro Kudo