Title:
ダイナミックランダムアクセスメモリアレイの電力を低減するための方法および集積回路装置
Document Type and Number:
Japanese Patent JP4853741
Kind Code:
B2
Abstract:
A low power Sleep Mode operation technique for dynamic random access (DRAM) devices and integrated circuit devices incorporating embedded DRAM. By counting clock (CLK) cycles in accordance with the technique disclosed, refresh time (tREF) does not vary with all possible process corners, voltages and temperatures (PVT) since the clock signal exhibits a steady frequency over PVT applied to the DRAM and an internal timer placed on chip will vary directly with these parameters. After entering Sleep Mode, the main internal clock signal is inhibited from propagating around the device chip and, at this time, much of the associated circuitry can be power-gated to conserve power, typically with signals that have a boosted level to provide a negative gate-to-source voltage (VGS) on the power-gating transistors.
Inventors:
Michael sey paris
Oscar Fredrick Jones, Jr.
Douglas Brain Butler
Oscar Fredrick Jones, Jr.
Douglas Brain Butler
Application Number:
JP2008216003A
Publication Date:
January 11, 2012
Filing Date:
August 25, 2008
Export Citation:
Assignee:
ソニー株式会社
International Classes:
G11C11/406; G11C8/00
Domestic Patent References:
| JP8147967A | ||||
| JP10208485A | ||||
| JP6282984A | ||||
| JP7235177A | ||||
| JP2001307484A | ||||
| JP2000195257A |
Attorney, Agent or Firm:
Yoichiro Fujishima
Yasushi Santanzaki
Masao Hasebe
Takaaki Tanaami
Longhua International Patent Service Corporation
Akihiro Ryuka
Yasushi Santanzaki
Masao Hasebe
Takaaki Tanaami
Longhua International Patent Service Corporation
Akihiro Ryuka