Title:
電力分析攻撃に安全な基本演算装置および方法
Document Type and Number:
Japanese Patent JP4885458
Kind Code:
B2
Abstract:
The circuit has a random data generator for generating random data, and a random mask device (100) for generating random mask data based on received input data and the random data. A logic device (300) executes a logic operation including the random mask data. The device outputs results of the logic operation in a random mask type and the logic operation not satisfying an associative law. An independent claim is also included for a method of executing a logic operation.
Inventors:
Elena Trichina
Yunju Chur
Yunju Chur
Application Number:
JP2005018876A
Publication Date:
February 29, 2012
Filing Date:
January 26, 2005
Export Citation:
Assignee:
Samsung Electronics Co.,Ltd.
International Classes:
H04L9/10; G06F7/58; H03K3/84; H03K19/20; H04L9/06
Domestic Patent References:
| JP2002141897A | ||||
| JP2000066585A | ||||
| JP2002366029A | ||||
| JP2003521201A | ||||
| JP2003513490A | ||||
| JP2002519722A |
Foreign References:
| WO2003060691A1 | ||||
| WO2001008012A1 | ||||
| WO2000067410A1 |
Other References:
E. Trichina,Combinational Logic Design for AES SubByte Transformation on Masked Data,Cryptology ePrint Archive,International Association for Cryptologic Research,2003年11月,Report 2003/236,[2010年12月22日検索],URL,http://eprint.iacr.org/2003/236
Y. Ishai, A. Sahai and D. Wagner,Private Circuits: Securing Hardware against Probing Attacks,Proceedings of CRYPTO 2003,2003年 8月,pp.463-481,[2010年12月22日検索],URL,http://www.iacr.org/cryptodb/archive/2003/CRYPTO/
Y. Ishai, A. Sahai and D. Wagner,Private Circuits: Securing Hardware against Probing Attacks,Proceedings of CRYPTO 2003,2003年 8月,pp.463-481,[2010年12月22日検索],URL,http://www.iacr.org/cryptodb/archive/2003/CRYPTO/
Attorney, Agent or Firm:
Masatake Shiga
Takashi Watanabe
Yasuhiko Murayama
Shinya Mitsuhiro
Takashi Watanabe
Yasuhiko Murayama
Shinya Mitsuhiro