Title:
金属層を有する半導体素子の形成方法
Document Type and Number:
Japanese Patent JP4891906
Kind Code:
B2
Abstract:
A metal layer is formed over a metal oxide, where the metal oxide is formed over a semiconductor substrate. A predetermined critical dimension of the metal layer is determined. A first etch is performed to etch the metal layer down to the metal oxide and form footings at the sidewalls of the metal layer. A second etch to remove the footings to target a predetermined critical dimension, wherein the second etch is selective to the metal oxide. In one embodiment, a conductive layer is formed over the metal layer. The bulk of the conductive layer may be etched leaving a portion in contact with the metal layer. Next, the portion left in contact with the metal layer may be etched using chemistry selective to the metal layer.
Inventors:
Stevens, Tab A.
Goulsby, Brian Jay.
Nguyen, Big-En
Ten, Boon-You
Goulsby, Brian Jay.
Nguyen, Big-En
Ten, Boon-You
Application Number:
JP2007532343A
Publication Date:
March 07, 2012
Filing Date:
August 23, 2005
Export Citation:
Assignee:
Freescale Semiconductor, Inc.
International Classes:
H01L21/3065; H01L21/28; H01L21/336; H01L29/423; H01L29/49; H01L29/78; H01L29/786
Domestic Patent References:
| JP2001160549A | 2001-06-12 | |||
| JP2004179612A | 2004-06-24 | |||
| JP2005285809A | 2005-10-13 | |||
| JP2004503106A | 2004-01-29 |
Attorney, Agent or Firm:
Mamoru Kuwagaki