Title:
半導体素子の実装方法及び半導体装置の製造方法
Document Type and Number:
Japanese Patent JP4946262
Kind Code:
B2
Abstract:
A mounting method of a semiconductor element whereby the semiconductor element is mounted on a wiring board via an outside connection projection electrode not containing lead (Pb), the mounting method includes a step of applying a reflow heating process for connecting the outside connection projection electrode of the semiconductor element and the wiring board and then cooling the connected semiconductor element and wiring board at a cooling rate equal to and lower than 0.5° C./s.
Inventors:
Joji Fujimori
Seiki Sakuyama
Toshiya Akamatsu
Seiki Sakuyama
Toshiya Akamatsu
Application Number:
JP2006223280A
Publication Date:
June 06, 2012
Filing Date:
August 18, 2006
Export Citation:
Assignee:
Fujitsu Semiconductor Limited
International Classes:
H01L21/60
Domestic Patent References:
| JP9092682A | ||||
| JP11195870A | ||||
| JP2006203096A | ||||
| JP2005005494A | ||||
| JP2004273654A | ||||
| JP10173005A | ||||
| JP8293665A |
Attorney, Agent or Firm:
Tadahiko Ito
Akinori Yamaguchi
Akinori Yamaguchi