Title:
絶縁ゲート型半導体装置
Document Type and Number:
Japanese Patent JP4957840
Kind Code:
B2
Abstract:
An insulated gate semiconductor device includes a semiconductor substrate, channel regions, floating regions, an emitter region, a body region, a hole stopper layer, and an emitter electrode. The channel regions and the floating regions are repeatedly arranged such that at least one floating region is located between adjacent channel regions. The emitter region and the body region are located in a surface portion of each channel region. The body region is deeper than the emitter region. The hole stopper layer is located in each floating region to divide the floating region into a first region and a second region. The emitter electrode is electrically connected to the emitter region and the first region.
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Inventors:
Kenji Kono
Yukio Tsuzuki
Yukio Tsuzuki
Application Number:
JP2010193473A
Publication Date:
June 20, 2012
Filing Date:
August 31, 2010
Export Citation:
Assignee:
株式会社デンソー
International Classes:
H01L29/78; H01L27/04; H01L29/739
Domestic Patent References:
| JP2004221370A | ||||
| JP2007266134A | ||||
| JP2005209811A | ||||
| JP2000307116A | ||||
| JP2009021557A | ||||
| JP2006295014A |
Attorney, Agent or Firm:
Patent Business Corporation Yuai Patent Office