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Title:
半導体装置、はんだバンプ接続用基板の製造方法及び半導体装置の製造方法
Document Type and Number:
Japanese Patent JP5017930
Kind Code:
B2
Abstract:

To provide a board connection structure for connecting boards via solder bumps which structure prevents short circuit between the solder bumps caused by deformation of the solder bumps, and connects the boards firmly using an underfill.

In the board connection structure, a pillarlike structure 4 made of an insulating material is disposed between the solder bumps 3 closest to each other, and a gap between the connected boards 1 and 2 is filled with the underfill 5. The deformed solder bumps 3 are blocked by the pillarlike structure 4 made of the insulating material, which prevents short circuit between the adjacent solder bumps 3. The plane of the pillarlike structure 4 and that of the solder bump 3 are separated from each other, so that the inflow of the underfill from the periphery of the structure 4 and solder bump 3 is not obstructed to allow firm connection through the underfill 5 with less voids.

COPYRIGHT: (C)2008,JPO&INPIT


Inventors:
Yoshikatsu Ishizuki
Application Number:
JP2006153835A
Publication Date:
September 05, 2012
Filing Date:
June 01, 2006
Export Citation:
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Assignee:
富士通株式会社
International Classes:
H01L21/60
Domestic Patent References:
JP1152637A
JP10189806A
JP2006100552A
JP2004134653A
JP2001351942A
JP61203648A
Attorney, Agent or Firm:
Junichi Yokoyama



 
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