Title:
時間-静止型プロセッサにおけるゼロ-オーバヘッドのブランチング及びルーピング
Document Type and Number:
Japanese Patent JP5068529
Kind Code:
B2
Abstract:
Programmable processors are used to transform input data into output data based on program information encoded in instructions. The value of the resulting output data depends, amongst others, on the momentary state of the processor at any given moment in time. This state is composed of temporary data values stored in registers, for example, as well as so-called flags. A disadvantage of the principle of flags, is that they cause side effects in the processor, especially in parallel processors. However, when removing the traditional concept of flags, the remaining problem is the implementation of branching. A processing system according to the invention comprises an execution unit (EX 1 , EX 2 ), a first register file (RF 1 , RF 2 ) for storing data, a memory (PM) and a second register file (RF 3 ) for storing a program counter. The execution unit conditionally executes dedicated instructions for writing a value of the program counter into the second register file. As a result, the processing system according to the invention allows conditional branching, without the use of flags.
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Inventors:
Jeroen Aye Reyeten
Application Number:
JP2006506909A
Publication Date:
November 07, 2012
Filing Date:
April 27, 2004
Export Citation:
Assignee:
Silicon Hive BV
International Classes:
G06F9/32; G06F9/30; G06F9/38
Domestic Patent References:
| JP60014338A | ||||
| JP10222367A | ||||
| JP10027102A | ||||
| JP2001229135A | ||||
| JP4096825A | ||||
| JP5020067A |
Foreign References:
| US20020032849 |
Other References:
Gert Goossens et al,"Embedded software in real-time signal processing systems: design technologies",Proceedings of the IEEE,Volume 85, Issue 3, March 1997,米国,IEEE,1997年 3月, Page(s):436 - 454
B.Ulmann,"μ-EP-1 a simple 32-bit architecture",Computer Architecture News, Association for Computing Machinery,米国,Special Interest Group on Computer Architecture,1995年 6月,Vol.23 No.3
B.Ulmann,"μ-EP-1 a simple 32-bit architecture",Computer Architecture News, Association for Computing Machinery,米国,Special Interest Group on Computer Architecture,1995年 6月,Vol.23 No.3
Attorney, Agent or Firm:
Hirohito Katsunuma
Yasukazu Sato
Yasushi Kawasaki
Takeshi Sekine
Akaoka Akira
Matsuno Chihiro
Yasukazu Sato
Yasushi Kawasaki
Takeshi Sekine
Akaoka Akira
Matsuno Chihiro