Title:
集積回路及びメモリテスト方法
Document Type and Number:
Japanese Patent JP5074968
Kind Code:
B2
Abstract:
An integrated circuit includes multiple memory circuits including memory cell arrays different in size, a BIST circuit which has a cell sequential transition test processor and which outputs a test cell address, a transition direction specification signal and an active signal. The integrated circuit has adjustment circuits which are provided respectively for the memory circuits and which replace the test cell address with the test cell address in a memory cell array area, or which convert the active signal into a signal indicating non-execution when the test cell address outputted from the BIST circuit corresponds to a cell in a virtual cell array being in an area outside the memory cell array.
Inventors:
Yasuyuki Hirasaki
Yoshitaka Aoki
Katsumi Shinbo
Yoshitaka Aoki
Katsumi Shinbo
Application Number:
JP2008069151A
Publication Date:
November 14, 2012
Filing Date:
March 18, 2008
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
G01R31/28; G11C29/12
Domestic Patent References:
| JP2006120241A | ||||
| JP11203893A | ||||
| JP2002222600A | ||||
| JP4229499A | ||||
| JP2002032999A | ||||
| JP6325600A |
Attorney, Agent or Firm:
Ken Ieiri