Title:
低K相互配線構造物用のしなやかな不動態化エッジシール
Document Type and Number:
Japanese Patent JP5147242
Kind Code:
B2
Abstract:
A structure for a chip or chip package is disclosed, with final passivation and terminal metallurgy which are mechanically decoupled but electrically coupled to the multilayer on-chip interconnects. This decoupling allows the chip to survive packaging stresses in the final passivation region, with strain relief from the decoupling region and compliant leads therein, so that on-chip interconnect levels do not feel these external packaging or other stresses. This structure is particularly preferred for on-chip interconnects consisting of Cu and low-k dielectric, the latter having inferior mechanical properties relative to SiO2. The decoupled region extends over all chips on the wafer. It may also extend into the edgeseal or dicing channel region so as to allow chip dicing and retention of this mechanical decoupling all around every chip on the wafer.
Inventors:
Edelstein, Daniel
Nicholson, Lee, M
Nicholson, Lee, M
Application Number:
JP2006549381A
Publication Date:
February 20, 2013
Filing Date:
January 06, 2005
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION
International Classes:
H01L23/12; H01L23/31
Domestic Patent References:
| JP2000150429A | ||||
| JP2000277465A | ||||
| JP2002050688A | ||||
| JP2003243401A |
Foreign References:
| US4017340 |
Attorney, Agent or Firm:
Takeshi Ueno
Tasaichi Tanae
Yoshihiro City
Hiroshi Sakaguchi
Tasaichi Tanae
Yoshihiro City
Hiroshi Sakaguchi