Title:
メモリアレイの動的ワードラインドライバ及びデコーダ
Document Type and Number:
Japanese Patent JP5362575
Kind Code:
B2
Abstract:
In a particular illustrative embodiment, a circuit device that includes first logic and second logic is disclosed. The first logic receives a clock signal and a first portion of a memory address of a memory array, decodes the first portion of the memory address, and selectively applies the clock signal to a selected group of wordline drivers associated with the memory array. The second logic decodes a second portion of the memory address and selectively activates a particular wordline driver of the selected group of wordline drivers according to the second portion of the memory address.
Inventors:
Phosphorus, Gents
Application Number:
JP2009532565A
Publication Date:
December 11, 2013
Filing Date:
October 10, 2007
Export Citation:
Assignee:
QUALCOMM INCORPORATED
International Classes:
G11C11/413; G11C11/418
Domestic Patent References:
| JP9050694A | ||||
| JP7192472A | ||||
| JP2006228294A | ||||
| JP62121989A | ||||
| JP6180991A | ||||
| JP4246913A | ||||
| JP2001135075A | ||||
| JP2002118455A | ||||
| JP4281294A |
Attorney, Agent or Firm:
Kurata Masatoshi
Yoshihiro Fukuhara
Makoto Nakamura
Nobuhisa Nogawa
Toshio Shirane
Takashi Mine
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Morisezo Iseki
Takao Ako
Tadashi Inoue
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori
Yoshihiro Fukuhara
Makoto Nakamura
Nobuhisa Nogawa
Toshio Shirane
Takashi Mine
Kocho Chojiro
Naoki Kono
Katsu Sunagawa
Morisezo Iseki
Takao Ako
Tadashi Inoue
Tatsushi Sato
Takashi Okada
Mihoko Horiuchi
Takenori Masanori