Title:
精密集積位相ロック回路用ループ・フィルタ
Document Type and Number:
Japanese Patent JP5385907
Kind Code:
B2
Abstract:
A loop filter in a phase lock loop circuit comprising a reference precision resistor, a first FET and a second FET, wherein the gate of the first FET is tied to the gate of the second FET, and a filter capacitor connected to the first FET for producing a capacitor voltage. The capacitor voltage is applied to the source of the first FET, the source of the second FET, and to the bottom of the reference precision resistor acting as a virtual ground. The capacitor voltage generated by the filter capacitor sets the bias point of the second FET such that the second FET comprises characteristics of an integrated precision resistor. A predetermined voltage generated by the second FET is applied to the gate of the first FET to set the bias point of the first FET such that the first FET comprises characteristics of an integrated precision resistor.
Inventors:
Bolstler, David, William
Qi, Jemin
Qi, Jemin
Application Number:
JP2010530383A
Publication Date:
January 08, 2014
Filing Date:
September 26, 2008
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION
International Classes:
H03H11/04; H03H11/40; H03L7/093
Domestic Patent References:
| JP2003204247A | ||||
| JP1141091A |
Attorney, Agent or Firm:
Takeshi Ueno
Tasaichi Tanae
Yoshihiro City
Tasaichi Tanae
Yoshihiro City
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