Title:
ゲートドライバ及びＥＬ表示装置
Document Type and Number:
Japanese Patent JP5401510
Kind Code:
B2
Abstract:
A circuit is provided which is constituted by TFTs of one conductivity type, and which is capable of outputting signals of a normal amplitude. When an input clock signal CK1 becomes a high level, each of TFTs (101, 103) is turned on to settle at a low level the potential at a signal output section (Out). A pulse is then input to a signal input section (In) and becomes high level. The gate potential of TFT (102) is increased to (VDD−V thN) and the gate is floated. TFT (102) is thus turned on. Then CK1 becomes low level and each of TFTs (101, 103) is turned off. Simultaneously, CK3 becomes high level and the potential at the signal output section is increased. Simultaneously, the potential at the gate of TFT (102) is increased to a level equal to or higher than (VDD+V thN) by the function of capacitor (104), so that the high level appearing at the signal output section (Out) becomes equal to VDD. When SP becomes low level; CK3 becomes low level; and CK1 becomes high level, the potential at the signal output section (Out) becomes low level again.
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Inventors:
Nagao 祥
Munehiro Asami
Yoshifumi Tanada
Munehiro Asami
Yoshifumi Tanada
Application Number:
JP2011148941A
Publication Date:
January 29, 2014
Filing Date:
July 05, 2011
Export Citation:
Assignee:
Incorporated company semiconductor energy research institute
International Classes:
G09G3/20; G09G3/30; G09G3/36; G11C19/00; G11C19/28; H03K3/356; H03K17/687; H03K19/017; H03K19/096