Title:
半導体装置の解析及び設計装置、及び半導体装置の解析及び設計方法
Document Type and Number:
Japanese Patent JP5405054
Kind Code:
B2
Abstract:
In a support apparatus for analysis and design of a semiconductor device, a function indicating an impurity concentration distribution in a channel region of a first transistor in a depth direction is set. A structure data indicating a structure of a transistor device and a measurement value of each of electric characteristics of the transistor are related. A Poisson's equation, which is express by using the function, is solved by using a depletion layer width as a variable to calculate a surface potential, and a first calculation value of the electric characteristic of the first transistor is calculated by using the surface potential. A determining section determines the function to indicate the impurity concentration distribution of a first transistor when a measurement value corresponding to a first structure data which indicates a structure of the first transistor, and the first calculation value are substantially coincident with each other.
More Like This:
Inventors:
Hironori Sakamoto
Application Number:
JP2008159701A
Publication Date:
February 05, 2014
Filing Date:
June 18, 2008
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H01L21/336; H01L29/00; H01L29/78
Domestic Patent References:
| JP2005340340A | ||||
| JP9148563A |
Other References:
M.Miura-Mattausch et al.,HiSIM2:Advanced MOSFET Model Valid For RF Circuit Simulation,IEEE Trans.On Electron Devices ,米国,IEEE,2006年 9月,Vol.53,No.9,pp.1994-2007
Attorney, Agent or Firm:
Minoru Kudo