Title:
半導体装置
Document Type and Number:
Japanese Patent JP5592599
Kind Code:
B2
Abstract:
A semiconductor memory device is constituted of a plurality of fuses (or anti-fuses) used for internal voltage adjustment or timing adjustment after manufacturing, a selector for sequentially selecting the fuses, and a single-direction latch circuit for latching a fuse breakdown determination result which is produced by determining whether or not each fuse selected by the selector is broken down and which is varied in a single direction from the low level to the high level or in a single direction from the high level to the low level. The semiconductor memory device allows the fuse breakdown determination to progress with a high reliability by use of a relatively small chip area and to cope with a failure in which one or more fuses are accidentally short-circuited to an unwanted potential.
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Inventors:
Junji Yamada
Application Number:
JP2008127706A
Publication Date:
September 17, 2014
Filing Date:
May 14, 2008
Export Citation:
Assignee:
P. S. Fau ルクスコ SARL PS4 Luxco S. a. r. l.
International Classes:
G11C29/00
Attorney, Agent or Firm:
Yamada Takuji