Title:
フォーカス制御回路
Document Type and Number:
Japanese Patent JP5626967
Kind Code:
B2
Abstract:
A first terminal supplies the bias voltage to a high-potential-side input terminal of a hall element. A second terminal supplies the ground potential to a low-potential-side input terminal of the hall element. A P-channel type transistor is configured such that the source terminal is connected to the power supply potential and the drain terminal is connected to the first terminal. An operational amplifier differentially amplifies the voltage between a predetermined set voltage and the voltage at the first terminal so as to control the gate voltage of the P-channel type transistor.
Inventors:
蔵 武
津田 廣之
神谷 知慶
永井 宏樹
津田 廣之
神谷 知慶
永井 宏樹
Application Number:
JP2010127596A
Publication Date:
November 19, 2014
Filing Date:
June 03, 2010
Export Citation:
Assignee:
セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー
International Classes:
G01D5/14; G01R33/07; G02B7/28; G03B13/36
Attorney, Agent or Firm:
Sakaki Morishita
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