Title:
半導体記憶装置、および、ビット線の充電方法
Document Type and Number:
Japanese Patent JP5644717
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To reduce power consumed by a return operation by appropriately setting a charging time of a bit line during returning from a low power consumption mode to a normal operation mode.SOLUTION: A semiconductor storage device 10 has a charge circuit 4 for respectively charging a plurality of bit lines 2a, 2b, ..., a ring oscillator 5 in which a dummy bit line 3 is used for wiring of a feedback path 5a, a counter 6 for outputting a detection signal when the number of oscillating times of the ring oscillator 5 reaches the predetermined number of times set on the basis of the number of the plurality of bit lines 2a, 2b, ..., and a control circuit 7 for making the charge circuit 4 start to charge the plurality of bit lines 2a, 2b, ... in response to a return signal instructing to return from the low power consumption mode to the normal operation mode, also making the ring oscillator 5 start oscillation, and making the charge circuit 4 finish charging the plurality of bit lines 2a, 2b, ... in response to a detection signal outputted from the counter 6.
Inventors:
下迫 孝治
芦澤 哲夫
芦澤 哲夫
Application Number:
JP2011180646A
Publication Date:
December 24, 2014
Filing Date:
August 22, 2011
Export Citation:
Assignee:
富士通セミコンダクター株式会社
International Classes:
G11C11/413
Attorney, Agent or Firm:
Kiyoshi Hattori
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