Title:
昇降圧回路及び昇降圧回路制御方法
Document Type and Number:
Japanese Patent JP5721403
Kind Code:
B2
Abstract:
A voltage boosting/lowering circuit according to an aspect of the present invention includes an output voltage generation circuit 15 that includes a switch element 2 connected between an input terminal 1 and a choke coil 3 and a switch element 7 connected between the choke coil 3 and a ground, and generates an output voltage by switching the switch elements 2 and 7 between an on-state and an off-state and thereby boosting/lowering an input voltage input to the input terminal 1, a first switch control unit that outputs a first pulse signal to the switch element 2, a duty detection circuit 32 that detects a duty of the first pulse signal, and a second switch control unit that outputs a second pulse signal to the switch element 7 according to the detected duty.
Inventors:
Uchiike Ken
Application Number:
JP2010257951A
Publication Date:
May 20, 2015
Filing Date:
November 18, 2010
Export Citation:
Assignee:
Renesas Electronics Corporation
International Classes:
H02M3/155
Domestic Patent References:
| JP2004208448A | ||||
| JP2007097361A | ||||
| JP2009124844A | ||||
| JP2003319644A |
Foreign References:
| US7777457 |
Attorney, Agent or Firm:
Ken Ieiri