Title:
半導体装置及びその製造方法
Document Type and Number:
Japanese Patent JP5755939
Kind Code:
B2
Abstract:
The invention is directed to a semiconductor device which is manufactured by a BiCMOS process in which a process of manufacturing a V-NPN transistor is rationalized. Furthermore, the hFE of the transistor is adjusted to a large value. An N type base width control layer is formed being in contact with a bottom portion of a P type base region under an N+ type emitter region. The N type base width control layer shallows a portion of the P type base region under the N+ type emitter region partially. The P type base region is formed by using a process of forming a P type well region, and the N type base width control layer is formed by using a process of forming an N type well region, thereby achieving the process rationalization.
More Like This:
| JPH02112271 | SEMICONDUCTOR DEVICE |
| JPS5911667 | INTEGRATED CIRCUIT |
| JP5578952 | A manufacturing method of a semiconductor device and a semiconductor device |
Inventors:
Seiji Otake
Application Number:
JP2011115618A
Publication Date:
July 29, 2015
Filing Date:
May 24, 2011
Export Citation:
Assignee:
Semiconductor Components Industries Limited Liability Company
International Classes:
H01L21/8249; H01L21/331; H01L21/8222; H01L21/8248; H01L27/06; H01L29/732
Domestic Patent References:
| JP56152258A | ||||
| JP5129535A | ||||
| JP1244660A | ||||
| JP8204041A | ||||
| JP2004311684A | ||||
| JP4370964A | ||||
| JP63164356A | ||||
| JP63269560A | ||||
| JP2003142613A | ||||
| JP2001274257A | ||||
| JP7335662A | ||||
| JP53067367A | ||||
| JP2003234423A |
Foreign References:
| US20040212043 |
Attorney, Agent or Firm:
Katsuhiko Sudo
Yasuhide Kamada
Yasuhide Kamada