Title:
同期化手段を備えた位相ロックループデバイス
Document Type and Number:
Japanese Patent JP5793213
Kind Code:
B2
Abstract:
A phase-locked loop (PLL) device (101) includes synchronization means (5, 50) suitable for synchronizing a frequency-converted signal produced by a frequency divider (4) of the PLL device, with a reference signal supplied to said PLL device. A time duration of a frequency/phase lock acquisition step which is performed upon starting an operation of the PLL device can be reduced. In addition, when operating several PLL devices simultaneously, the synchronization means allow recovering target values for phase differences that exist between the respective frequency-converted signals of the PLL devices. To this end, synchronization is requested at a same time for all the PLL devices after they are all running in locked state.
Inventors:
Fabrice Hovenin
Cedric Moran
Cedric Moran
Application Number:
JP2014069659A
Publication Date:
October 14, 2015
Filing Date:
March 28, 2014
Export Citation:
Assignee:
Asahi Kasei Electronics Co., Ltd.
International Classes:
H03L7/199; H03K5/26; H03L7/22
Domestic Patent References:
| JP6021811A | ||||
| JP10308667A | ||||
| JP2262717A | ||||
| JP5063565A | ||||
| JP2004193901A |
Foreign References:
| US6285260 |
Attorney, Agent or Firm:
Patent Business Corporation Tani/Abe Patent Office