Title:
マルチプロセッサシステムにおける通信の無効化
Document Type and Number:
Japanese Patent JP5815717
Kind Code:
B2
Abstract:
Disabling communication in a multiprocessor fabric. The multiprocessor fabric may include a plurality of processors and a plurality of communication elements and each of the plurality of communication elements may include a memory. A configuration may be received for the multiprocessor fabric, which specifies disabling of communication paths between one or more of: one or more processors and one or more communication elements; one or more processors and one or more other processors; or one or more communication elements and one or more other communication elements. Accordingly, the multiprocessor fabric may be automatically configured in hardware to disable the communication paths specified by the configuration. The multiprocessor fabric may be operated to execute a software application according to the configuration.
Inventors:
Dore, Michael Bee
Dobbs, Karl S
Solka, Michael Bee
Trosino, Michael Earl
Gibson, David A
Dobbs, Karl S
Solka, Michael Bee
Trosino, Michael Earl
Gibson, David A
Application Number:
JP2013534050A
Publication Date:
November 17, 2015
Filing Date:
October 14, 2011
Export Citation:
Assignee:
Coherent Logics Incorporated
International Classes:
G06F21/71; G06F12/14; G06F21/60
Domestic Patent References:
| JP2005531089A | ||||
| JP2000132530A | ||||
| JP5113961A | ||||
| JP2003108257A |
Foreign References:
| US7246217 |
Attorney, Agent or Firm:
Masaki Yamakawa
Shigeki Yamakawa
Shigeki Yamakawa
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