Title:
三次元構造を有する薄膜トランジスタ及びその製造方法
Document Type and Number:
Japanese Patent JP5887591
Kind Code:
B2
Abstract:
This invention is provided with: an insulating substrate (1); a step structure (2) forming a convex surface with respect to the principal surface (1a) of the substrate and having a side wall surface (2a) which is oriented vertically in relation to the principal surface; a gate electrode layer (3) provided along the side wall surface; a gate insulator layer (4) provided so as to cover the gate electrode layer; a semiconductor layer (5) provided on the gate insulator layer in at least a region along the side wall surface; a source electrode (6) arranged in one of two areas selected from the upper part of the step structure and the region of the substrate that excludes the step structure; and a drain electrode (7) arranged on the other of the two areas; each of the source electrode and the drain electrode being formed so as to connect to the semiconductor layer in areas at top and bottom ends of the side wall surface. The transistor is configured so that the semiconductor layer is provided along the side wall surface, which is oriented vertically to the principal surface of the substrate, and the parasitic capacitance between the gate electrode and the source/drain electrodes is minimized.
Inventors:
Junichi Takeya
Mayumi Uno
Mayumi Uno
Application Number:
JP2012027505A
Publication Date:
March 16, 2016
Filing Date:
February 10, 2012
Export Citation:
Assignee:
Pai Crystal Co., Ltd.
Osaka Prefectural Industrial Technology Research Institute
Osaka Prefectural Industrial Technology Research Institute
International Classes:
H01L29/786; H01L21/28; H01L21/3065; H01L21/336; H01L29/41; H01L29/423; H01L29/49
Domestic Patent References:
| JP2005019446A | ||||
| JP2003282884A |
Foreign References:
| WO2009133891A1 |
Attorney, Agent or Firm:
Ikeuchi, Sato & Partners