Title:
半導体装置
Document Type and Number:
Japanese Patent JP5921838
Kind Code:
B2
Abstract:
A structure with which the zero current of a field effect transistor using a conductor-semiconductor junction can be reduced is provided. A floating electrode (102) including a conductor or a semiconductor and being enclosed by an insulator (104) is formed between a semiconductor layer (101) and a gate (105) so as to cross the semiconductor layer (101) and the floating electrode (102) is charged, whereby carriers are prevented from flowing from a source electrode (103a) or a drain electrode (103b). Accordingly, a sufficiently low carrier concentration can be kept in the semiconductor layer (101) and thus the zero current can be reduced.
Inventors:
Yasuhiko Takemura
Application Number:
JP2011192413A
Publication Date:
May 24, 2016
Filing Date:
September 05, 2011
Export Citation:
Assignee:
Semiconductor Energy Laboratory Co., Ltd.
International Classes:
H01L21/336; H01L21/8242; H01L21/8247; H01L27/108; H01L27/115; H01L29/786; H01L29/788; H01L29/792
Domestic Patent References:
| JP7249688A | ||||
| JP2009060087A | ||||
| JP2007318112A | ||||
| JP2007250983A | ||||
| JP57007162A | ||||
| JP2011151370A | ||||
| JP2007318109A |